A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

by: Zhongfeng Wang, Zhiqiang Cui

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 15, No. 4. (2007), pp. 483-488.

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<para> This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems. </para>

@article{citeulike:1273116, abstract = {<para> This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30\% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems. </para>}, author = {Wang, Zhongfeng and Cui, Zhiqiang }, citeulike-article-id = {1273116}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, number = {4}, pages = {483--488}, posted-at = {2007-05-03 04:55:57}, priority = {2}, title = {A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=4162517}, volume = {15}, year = {2007} }

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TY - JOUR ID - citeulike:1273116 L3 - citeulike-article-id:1273116 TI - A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes JF - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on VL - 15 IS - 4 SP - 483 EP - 488 N2 - <para> This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems. </para> AU - Wang, Zhongfeng AU - Cui, Zhiqiang PY - 2007/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4162517 ER -

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